Method for backend physical design and circuit layout

A circuit backend physical design method, comprising:

• performing automatic placement and routing (APR) according to a gate-level netlist file to generate a graphic data system (GDS) file, wherein the GDS file comprises a circuit layout;
• performing dummy metal insertion on the circuit layout to add dummy metal into the circuit layout to generate a first updated GDS file, which comprises the circuit layout and the dummy metal;
• performing static timing analysis on the updated GDS file to generate a timing report;
• if the timing report indicates that a critical path has a timing violation, configuring a dummy blockage around the critical path of the circuit layout of the GDS file;
• and
• performing a dummy metal insertion on the circuit layout to add dummy metal into the circuit layout, wherein dummy metal is not added to a region of the dummy blockage in the circuit layout, so as to generate a second updated GDS file, which comprises the circuit layout and the dummy metal.

A circuit layout, comprising:

• a first area, comprising a critical path;
• and
• a second area, not comprising any critical path;
• wherein a metal density of the first area is lower than a metal density of the second area.