A method for securing a central processing unit pipeline

A method for securing a central processing unit pipeline comprising the steps of

• providing a central processing unit (CPU), the central processing unit comprising a fetcher, a decoder and means for executing computer program instructions decoded by the decoder;
• allowing an instruction of a computer program to be fetched by the fetcher of the central processing unit;
• allowing the decoder of the central processing unit to decode the instruction fetched in order to obtain a decoded instruction structure;
• allowing the means for executing the instruction to execute the instruction according to its decoded structure;
• providing an integrity pipeline supervisor (IPS), the integrity pipeline supervisor comprising a decoder and a checker;
• providing the integrity pipeline supervisor with the instruction of the computer program;
• allowing the decoder of the integrity pipeline supervisor to decode the instruction provided to the integrity pipeline supervisor in order to obtain the decoded instruction structure;
• providing the checker with the structure of the decoded instruction by the decoder of the integrity pipeline supervisor;
• providing the checker with the structure of the instruction decoded by the decoder of the central processing unit;
• allowing the checker to compare the structure of the instruction decoded by the decoder of the integrity pipeline supervisor and the structure of the instruction decoded by the decoder of the central processing unit;
• and
• allowing an alarm indicator to be triggered if, as a result of the comparison, the checker detects a discrepancy between the structure of the instruction decoded by the decoder of the integrity pipeline supervisor and the structure of the instruction decoded by the decoder of the central processing unit.