Cryptocurrency miner and device enumeration
AssigneeChain Reaction, Ltd.
InventorsMichael Tal, Gil Shefer, Rony Gutierrez
Life of this patent
Estimating the term…
Abstract
A cryptocurrency miner includes a serial bus, compute modules, and a controller. Each compute module includes upstream ports, downstream ports, a pass-through buffer coupling the upstream ports to the downstream ports, and a serial bus interface coupled to the serial bus via the first upstream ports and the first downstream ports. The controller controls operation of the compute modules via commands on the serial bus. The serial bus includes bus segments between respective upstream and downstream ports of the compute modules.
Claims20
A computing device, comprising:
- a controller;
- a first compute board comprising a board and compute chips coupled to the board;
- and
- bus segments of one or more busses that couple the controller to each compute chip of the first compute board;
- wherein each compute chip of the first compute board comprises one or more compute engines and a plurality of address registers;
- wherein the controller is configured to issue a first write command to a first compute chip of the first compute board via a first path through the bus segments;
- and
- wherein the first compute chip is configured to write a plurality of different addresses provided by the first write command to the plurality of address registers of the first compute chip in response to the first compute chip determining that the first write command is directed to an address stored by at least one of the address registers of the first compute chip.
A method of a computing device, the method comprising:
- issuing, from a controller of the computing device, a first write command to a first compute chip of a first compute board via a first path through bus segments of one or more busses;
- receiving, with the first compute chip, the first write command via the first path through the bus segments;
- and
- writing, with the first compute chip, a plurality of different addresses provided by the first write command to a plurality of address registers of the first compute chip in response to determining that the first write command is directed to an address stored by at least one address register of the first compute chip.
Dependencies are inferred from the claim text.