Intent-Based CXL Translations for Inter-Entity Cache State Coordination in Heterogeneous Computing Platforms

Abstract

Identifying cacheline state intent across protocols may enable cache-coherent interoperability for AI training and inference platforms coupling heterogeneous processors, accelerators, and memory pools via CXL. Implementations include receiving a first CXL message from a first entity, identifying a cacheline state intent based on at least one of an opcode or a SnpType of the first CXL message, wherein the cacheline state intent pertains to a cacheline address specified in the first CXL message, translating the first CXL message to a second CXL message comprising an opcode selected based on the identified cacheline state intent, and sending the second CXL message to a second entity. Optionally, the translation enables H2D request to D2H request conversion or CXL.mem to CXL.cache bridging. Optionally, a cache abstraction is exposed as a proxy for cache resources maintained by the second entity. Optionally, cacheline state orchestration enables cache-coherent memory sharing between the entities.

Dependencies are inferred from the claim text.