US 2026/0228008 A1 · ON-CHIP DECOMPRESSION AND SPARSITY DECODE

Abstract

Techniques for decompression and sparsity decoding are described. Examples detailed herein utilize a matrix data micro-engine invoked by an instruction and configured using a descriptor. The matrix data micro-engine pulls in data from memory (e.g., in a stream of blocks) and processes this data to make it ready for computational hardware. This effectively decouples the memory access patterns from the compute cadence. The use of the descriptor allows for complex, multi-stage data transformations (e.g., INT4 to FP16 conversion, 2:4 sparsity expansion, and layout transposition) to occur strictly within the hardware data path (stream decompressor and sparsity mask decoder) without polluting the instruction cache with decompression code or burdening the main CPU pipeline.

Claims21

Dependent claims

An apparatus comprising:

decoder circuitry to decode an instance of a single instruction, the instance of the single instruction has at least one field for an opcode and at least one field to identify a location in memory that is to store a descriptor;
and
execution circuitry to execute the decoded instruction according to the opcode to at least prefetch the descriptor, interpret fields of the descriptor, prefetch packed blocks representing matrix data from memory, decode and/or decompress the packed blocks, generate one or more index/value tokens or dense matrices based on sparsity metadata, and buffer the one or more index/value tokens or dense matrices based on sparsity metadata into a destination.

Dependencies are inferred from the claim text.

On-chip decompression and sparsity decode

Life of this patent

On-chip decompression and sparsity decode

Life of this patent

Abstract

Claims21