Methods of manufacturing superconducting via through semiconductor wafer

Abstract

A method of manufacturing a superconducting via through a semiconductor wafer having opposed first and second surfaces. The method comprises: (A) forming, at least partly, a via extending through the semiconductor wafer from the first surface to the second surface by etching into the first surface of the semiconductor wafer using a first plasma etching process; and then: (B) using a second plasma etching process different from the first plasma etching process, etching the wall of the via so as to reduce its surface roughness; (C) after step (B), depositing a superconductor material on at least a portion of the wall of the via; and (D) if the via was not formed completely in step (A), completing the formation of the via such that the via extends from the first surface to the second surface of the semiconductor wafer; whereby the deposited superconductor material forms an electrically conductive pathway electrically connecting the first and second surfaces of the semiconductor wafer.

Dependencies are inferred from the claim text.