Dual-port memory with charge sharing mitigation

An apparatus, comprising:

• a memory circuit including a first port and a second port;
• and
• a first circuit coupled to the memory circuit via the first port and the second port, the first circuit configured to supply first signals to the first port to write to a memory cell of the memory circuit and second signals to the second port to read from the memory cell;
• wherein the memory cell is coupled to a first bit line and a second bit line, the first bit line and the second bit line coupled to a first node of the memory cell;
• wherein the memory circuit includes a controller, the controller comprising a first write driver coupled to the first bit line and a second write driver coupled to the second bit line, the first write driver configured to, during a first time interval, apply a first voltage to the first bit line in response to a first control signal and a first data signal, the second write driver configured to, during the first time interval, apply the first voltage to the second bit line in response to a second control signal and the first data signal.

A method of driving a memory cell in a dual-port memory circuit, comprising:

• charging a first row line to turn on a first switch of the memory cell that couples a first bit line to a first node of the memory cell;
• charging a second row line to turn on a second switch of the memory cell that couples a second bit line to the first node;
• applying, by a first write driver during a first time interval, a first voltage to the first bit line in response to a first control signal and a first data signal;
• and
• applying, by a second write driver during the first time interval, the first voltage to the second bit line in response to a second control signal and the first data signal.