Polymorphic system level cache having local vector processing
AssigneeQUALCOMM Incorporated
InventorsMahdi NAZM BOJNORDI, Paul Nicholas WHATMOUGH
Life of this patent
Estimating the term…
Abstract
Techniques described herein include a polymorphic system level cache. The polymorphic system level cache includes a cache controller and plurality of banks. The cache controller is configured to control operation of each of the plurality of banks. At least one bank of the plurality of banks includes: a data array; a local register communicatively coupled to data array; and an arithmetic logic unit array communicatively coupled to the local register and the data array.
Claims20
An apparatus, comprising:
- a system level cache comprising a cache controller and plurality of banks, the cache controller configured to control operation of each of the plurality of banks, at least one bank of the plurality of banks comprising:
- a data array;
- a local register communicatively coupled to data array;
- and
- an arithmetic logic unit array communicatively coupled to the local register and the data array.
A method performed by a system level cache included in a system-on-chip, comprising:
- receiving a request to access the system level cache, the request including an address range corresponding to an address range for a respective bank of a plurality of banks of the system level cache;
- determining a non-cache operation mode as a selected operation mode for the respective bank of the plurality of banks;
- and
- accessing the respective bank of the system level cache according to the selected operation mode, wherein the accessing comprises performing one or more vector operations using an arithmetic logic unit array that is included in the respective bank of the system level cache.
An apparatus, comprising:
- means for receiving a request to access a system level cache, the request including an address range corresponding to an address range for a respective bank of a plurality of banks of the system level cache;
- means for determining a non-cache operation mode as a selected operation mode for the respective bank of the plurality of banks;
- and
- means for accessing the respective bank of the system level cache according to the selected operation mode, wherein the accessing comprises performing one or more vector operations using an arithmetic logic unit array that is included in the respective bank of the system level cache.
Dependencies are inferred from the claim text.