Memory system

A semiconductor storage device comprising:

• a first signal pad;
• a second signal pad;
• a third signal pad;
• a memory cell array including a string, the string including a plurality of memory cell transistors connected in series;
• a status register configured to store ready/busy data indicating a ready/busy state of the semiconductor storage device;
• and
• a sequencer configured to
• in response to a read command received through the first and second signal pads, perform a read operation on one of the memory cell transistors and update the ready/busy data to indicate a busy state,
• upon completion of the read operation, update the ready/busy data to indicate a ready state, and
• in response to a status output instruction received through the first and second signal pads while an enable signal received through the third signal pad is set to a first level, continue outputting the ready/busy data through the first signal pad while allowing an input through the second signal pad,
• in response to a change in the enable signal from the first level to a second level, stop outputting the ready/busy data through the first signal pad.