System and method for detecting deviations in hardware timers
AssigneeMicrochip Technology Incorporated
InventorDaniel Costin
Life of this patent
Estimating the term…
Abstract
Systems and methods are disclosed for detecting deviations in hardware timer operations. A system may include a first timer driven by a first clock source to produce a first timer value, while a second timer may be driven by a second, independent clock source to produce a second timer value. A deviation logic hardware block may compute a complement of the first timer value, calculate a difference between the complemented value and the second timer value, and compare the difference to a deviation limit to determine whether a deviation has occurred.
Claims20
A system for detecting deviations in hardware timer operations, comprising:
- a first timer configured to be driven by a first clock source and to output a first timer value;
- a second timer configured to be driven by a second clock source, independent of the first clock source, and to output a second timer value;
- a deviation logic hardware block (DLHB) to:
- compute a complement of the first timer value;
- calculate a difference between the complement of the first timer value and the second timer value;
- and
- compare the difference to a predefined deviation limit to determine whether a deviation has occurred.
A method for detecting deviations in hardware timer operations, the method comprising:
- driving a first timer with a first clock source to output a first timer value;
- driving a second timer with a second clock source, independent of the first clock source, to output a second timer value;
- computing a complement of the first timer value;
- calculating a difference between the complement of the first timer value and the second timer value;
- comparing the calculated difference to a predefined deviation limit;
- and
- generating a deviation flag in response to determining that the calculated difference exceeds the predefined deviation limit.
An apparatus for detecting deviations in timer operations, the apparatus comprising:
- a first timer configured to be driven by a first clock source and output a first timer value;
- a first period register to store a first threshold;
- a first comparator to compare the first timer value to the first threshold;
- an event interrupt circuit to generate an interrupt signal in response to the first timer value matching the first threshold;
- a second timer configured to be driven by a second clock source, independent of the first clock source, and to output a second timer value;
- a deviation logic hardware block (DLHB) to:
- compute a complement of the first timer value;
- calculate a difference between the complement of the first timer value and the second timer value;
- and
- compare the difference to a predefined deviation limit to determine whether a deviation has occurred;
- and
- a first logic circuit to generate a valid timer interrupt in response to the interrupt signal and determining that a deviation has not occurred.
Dependencies are inferred from the claim text.