Latching system and method for low soft error rate
AssigneeAvago Technologies International Sales Pte. Limited
InventorsKarthik CHANDRASEKHARAN, Balaji NARASIMHAM
Life of this patent
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Abstract
Systems for and methods of reducing soft errors can be utilized in any circuit. A circuit can include a first inverter having a first inverter input and a first inverter output, a second inverter having a second inverter input and a second inverter output, and a soft error hardening circuit. The first inverter input is coupled to the second inverter output, and the second inverter input is coupled to the first inverter output. The clock input is configured to receive a clock signal. The soft error hardening circuit is coupled to the first inverter and/or the second inverter.
Claims20
A circuit, comprising:
- a first inverter having a first inverter input and a first inverter output;
- a second inverter having a second inverter input, a clock input, and a second inverter output, the first inverter input being coupled to the second inverter output, the second inverter input being coupled to the first inverter output, the clock input being configured to receive a clock signal;
- and
- a soft error hardening circuit coupled to the first inverter and the second inverter.
A circuit, comprising:
- a first inverter having a first inverter input and a first inverter output, wherein the first inverter is comprised of a first pair of first transistors and a second pair of second transistors coupled in series, wherein gates of the first pair and the second pair are coupled to the first inverter input and wherein a first node is between the first pair of the first transistors and a second node is between the second pair of the second transistors;
- a second inverter having a second inverter input, and a second inverter output, the first inverter input being coupled to the second inverter output, the second inverter input being coupled to the first inverter output;
- and
- a soft error hardening circuit coupled to the first node or the second node or to both the first node and the second node.
A circuit, comprising:
- a first inverter having a first inverter input and a first inverter output, wherein the first inverter is comprised of a first pair of first transistors and a second pair of second transistors coupled in series, wherein gates of the first pair and the second pair are coupled to the first inverter input;
- a second inverter having a second inverter input, and a second inverter output, the first inverter input being coupled to the second inverter output, the second inverter input being coupled to the first inverter output;
- and
- a soft error hardening circuit comprising one or more diodes, wherein the circuit is configured so that a first diode is switched on and off by a data state provided to the first inverter input or the second inverter input.
Dependencies are inferred from the claim text.