Gate driver, display device including the gate driver, and electronic apparatus including the display device

A display device comprising:

• a display panel comprising a plurality of pixel rows, each of the plurality of pixel rows comprises a plurality of pixels;
• and
• a gate driver comprising a plurality of stages, the plurality of stages are configured to output gate signals to the plurality of pixel rows,
• wherein each of the plurality of stages comprises:
• an input transistor configured to transmit an input signal to a Q node in response to a clock signal;
• an output terminal to output an output signal, the output terminal is disposed between a pull-up transistor and each of a first pull-down transistor and a second pull-down transistor,
• the pull-up transistor configured to output a high gate voltage as the output signal in response to a signal of a QB node, the QB node is connected to a gate of the pull-up transistor,
• the first pull-down transistor configured to output a low gate voltage as the output signal in response to a signal of the Q node, and
• the second pull-down transistor is configured to output the low gate voltage as the output signal in response to a signal of a B node, the B node is connected to a gate of the second pull-down transistor;
• and
• a first control transistor configured to transmit a signal of a QB node of a previous stage to the B node in response to the signal of the Q node, the Q node is connected to both of a gate of the first pull-down transistor and a gate of the first control transistor.

An electronic apparatus comprising:

• a display device;
• and
• a processor configured to control the display device,
• wherein the display device comprises:
• a display panel comprising a plurality of pixel rows, each of the plurality of pixel rows comprises a plurality of pixels;
• and
• a gate driver comprising a plurality of stages, the plurality of stages are configured to output gate signals to the plurality of pixel rows,
• wherein each of the plurality of stages comprises:
• an input transistor configured to transmit an input signal to a Q node in response to a clock signal;
• an output terminal to output an output signal, the output terminal is disposed between a pull-up transistor and each of a first pull-down transistor and a second pull-down transistor;
• the pull-up transistor configured to output a high gate voltage as the output signal in response to a signal of a QB node, the QB node is connected to a gate of the pull-up transistor;
• the first pull-down transistor configured to output a low gate voltage as the output signal in response to a signal of the Q node;
• the second pull-down transistor is configured to output the low gate voltage as the output signal in response to a signal of a B node, the B node is connected to a gate of the second pull-down transistor;
• and
• a first control transistor configured to transmit a signal of a QB node of a previous stage to the B node in response to the signal of the Q node, the Q node is connected to both of a gate of the first pull-down transistor and a gate of the first control transistor.