US 2026/0206298 A1Published application

Trench power semiconductor device

AssigneeExcelliance MOS Corporation

InventorsChu-Kuang Liu, Yun-Han Cheng

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Abstract

A trench power semiconductor device includes a substrate, an epitaxial layer, a first gate structure, a second gate structure, a body region, a first source region, and a second source region. The epitaxial layer is on the substrate and has first trenches and second trenches alternatively arranged. The first gate structure is disposed within each first trench to form MCD elements. The second gate structure is disposed within each second trench to form MOS elements. The body region is formed in the epitaxial layer and between the first trenches and the second trenches. The first source region is formed in the body region at two sides of each first trench. The second source region is formed in the body region at two sides of each second trench. A bottom surface of the first source region is not lower than a bottom surface of the second source region.

Claims10

Dependent claims

A trench power semiconductor device, comprising:

a substrate;
an epitaxial layer, located on the substrate, wherein the epitaxial layer has a plurality of first trenches and a plurality of second trenches alternately arranged;
a first gate structure, disposed within each of the plurality of first trenches, to form a MOS controlled diode (MCD) element;
a second gate structure, disposed within each of the plurality of second trenches, to form a MOS element;
a body region, formed in the epitaxial layer and located between the plurality of first trenches and the plurality of second trenches;
a first source region, formed in the body region at two sides of each of the plurality of first trenches;
and
a second source region, formed in the body region at two sides of each of the plurality of second trenches, and connected to the first source region,
wherein a bottom surface of the first source region is not lower than a bottom surface of the second source region.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/047,649Filed 7 Feb 2025
Priority: TW 11410118910 Jan 2025
Published: 16 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification29 codes

H10D 84/8314
Of only insulated-gate FETs [IGFET]: the IGFETs characterised by having gate insulating layers with different properties
H10D 12/211
Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]: gated diodes
H10D 30/0295
Of vertical dmos [vdmos] fets: using recessing of the source electrodes
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes

Family

No related US applications are recorded in the indexed filing history.

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