Selection summing latch circuit for a decision feedback equalizer

A selection summing latch circuit for a decision feedback equalizer, characterized in that the selection summing latch circuit comprises a selection summing unit, a latch amplifier, a sampler and a resetter;

• the selection summing unit is configured to selectively select a positive reference voltage or a negative reference voltage to sum with an input signal according to the logic levels of a positive selection signal terminal and a negative selection signal terminal to obtain a summation result when a sampling clock is at a high level;
• the latch amplifier is configured to latch and amplify the summation result and output an output result to a positive output signal terminal and a negative output signal terminal when the sampling clock is at a high level;
• the sampler is configured to sample the selection summing unit when the sampling clock is at a high level;
• the resetter is configured to reset the positive output signal terminal and the negative output signal terminal when the sampling clock is at a low level.