Digital phase-locked loops (pll) including closed-loop time-to-digital converter (tdc) gain calibration circuits and related methods

A method of operating a calibrated digital phase-locked loop (DPLL), comprising:

• generating, in a digitally controlled oscillator (DCO) circuit, a first output clock having a first frequency based on a control value;
• and
• in a feedback circuit:
• in a normal operating mode:
• generating a first measurement of a first time interval corresponding to a phase difference between the first output clock and a reference clock;
• and
• updating the control value based on the first measurement;
• and
• in a calibration operating mode:
• keeping the control value constant;
• and
• adjusting a first resolution of the first measurement to be closer to a nominal resolution.

An integrated circuit (IC), comprising a plurality of clock domains each comprising:

• a calibrated digital phase-locked loop (DPLL), comprising:
• a digitally controlled oscillator (DCO) circuit configured to generate a first output clock having a first frequency based on a control value;
• and
• a feedback circuit configured to:
• in a normal operating mode:
• generate a first measurement of a first time interval corresponding to a phase difference between the first output clock and a reference clock;
• and
• update the control value based on the first measurement;
• and
• In a calibration operating mode:
• keep the control value constant;
• and
• adjust a first resolution of the first measurement to be closer to a nominal resolution;
• and
• a plurality of digital logic circuits configured to operate in response to the first output clock,
• wherein the plurality of digital logic circuits of a first clock domain of the plurality of clock domains are configured to communicate with the plurality of digital logic circuits of a second clock domain of the plurality of clock domains.