Low phase noise phase locked loop

A signal generator, comprising:

• a controlled oscillator circuit configured to generate an output signal having an output signal frequency based on a control input signal;
• a frequency divider circuit configured to produce a divided frequency output having a frequency equal to the output signal frequency divided by a value;
• a phase frequency detector circuit configured to produce a phase error signal based on a phase difference between the divided frequency output and a frequency reference signal;
• a Phase Locked Loop (PLL) filter circuit configured to generate a low pass filtered error signal with a frequency based on low pass filtering the phase error signal;
• a tunable Inductor-Capacitor (LC) time reference circuit configured to generate a time reference signal with a frequency based on a combination of a series connected inductor and capacitor, a signal based on the output signal, and the low pass filtered error signal;
• and
• a time error detector circuit configured to determine a filtered time error signal indicating a time error between a level transition of a signal based on the output signal and a level transition of the time reference signal,
• wherein the time error detector circuit comprises a sample and hold circuit configured to determine the time error based on a time difference between an occurrence of the level transition of the signal based on the output signal and the level transition of a signal based on the time reference signal, and
• wherein the control input signal is based on the filtered time error signal.