Processing of ternary symbols

A device for processing a value determined from a set of N ternary memory cells, wherein the device is configured to

• read out the set of ternary memory cells from a memory and determine the ternary symbol H, M or L contained in the respective ternary memory cell,
• determine a first binary sequence based on the ternary symbols H of the set of read ternary memory cells,
• determine a second binary sequence based on the ternary symbols H and M of the set of read ternary memory cells,
• determine a third binary sequence based on the first binary sequence and the second binary sequence, wherein the number of bits in the third binary sequence is reduced compared with the number of bits in the first binary sequence and the second binary sequence,
• determine a composite binary value based on the first binary sequence and the third binary sequence, and
• process the composite binary value.

A device, comprising:

• a combinational circuit configured to generate n−1 control signals based on n binary values of a first binary sequence, wherein the first binary sequence is indicative of memory cells in a set of n memory cells storing the ternary symbol H;
• and
• n−1 multiplexers, controlled by respective control signals to output selected bits of a second binary sequence comprising n binary values to generate a third binary sequence of n−1 values, wherein the second binary sequence is indicative of memory cells in the set of n memory cells storing either the ternary symbol H or the ternary symbol M,
• wherein the device is configured to determine a composite binary value based on the first binary sequence and the third binary sequence.