Device and method with instruction-based computing

Abstract

A computing device includes a memory configured to store input data and a plurality of instructions, a processor configured to execute instructions of a predetermined length among the plurality of instructions received from the memory, a command queue configured to receive, from the processor, instructions corresponding to an accelerator among the instructions of the predetermined length and generate a merged instruction by merging the received instructions through an arithmetic logic unit (ALU), and the accelerator configured to perform an operation between the input data and pre-stored data in response to receiving the merged instruction from the command queue.

Dependencies are inferred from the claim text.