Hybrid channel semiconductor device and method of fabricating the same

A method of fabricating a semiconductor device, the method comprising:

• forming a first source/drain structure and a second source/drain structure spaced apart in a first direction on a substrate;
• forming at least first and second channel structures spaced apart relative to a second direction perpendicular to the substrate, the first channel structure being an uppermost channel structure of the at least first and second channel structures,
• wherein the first and second source/drain structures and the at least first and second channel structures are formed such that the first and second source/drain structures have the at least first and second channel structures therebetween;
• removing part of the first channel structure such that a first portion of the first channel structure remains adjacent the first source/drain structure at a first distance from the substrate, and a second portion of the first channel structure remains adjacent the second source/drain structure at the first distance from the substrate and spaced apart from the first portion of the first channel structure in the first direction;
• and
• forming an insulating structure between the first and second portions of the first channel structure relative to the first direction, the insulating structure being at the first distance from the substrate and being formed to have a thickness that is at least as thick as either of the first and second portions of the first channel structure.

A semiconductor device comprising:

• a first stack of a number n of channel structures that is greater than 1, the n channel structures being spaced apart in a vertical direction;
• a first gate at least partially surrounding the n channel structures;
• a second stack of a number n-1 of channel structures, the n-1 channel structures being spaced apart in the vertical direction;
• a second gate at least partially surrounding the n-1 channel structures;
• a first source/drain structure at a first side of the second gate and a second source/drain structure at a second side of the second gate, the n-1 channel structures being configured to selectively conduct current between the first and second source/drain structures;
• and
• an insulating structure at least partially surrounded by the second gate, the insulating structure being between the first and second source/drain structures at a same level as an uppermost channel structure of the n channel structures in the first stack of n channel structures, the insulating structure blocking a current path between the first and second source/drain structures at a level of the uppermost channel structure.