Low power flip-flop and integrated circuit including the same

A flip-flop configured to generate a data output by latching a data input based on a clock input, the flip-flop comprising:

• a master latch configured to generate, based on the data input and the clock input, a first data signal complementary to the data input, a second data signal complementary to the first data signal, and a clock signal complementary to the clock input;
• and
• a slave latch configured to receive the clock signal through a first node and to generate the data output by latching a third data signal based on the clock input, the second data signal, and the clock signal, the third data signal being complementary to the second data signal,
• wherein the master latch is further configured to float the first node based on the first data signal and the third data signal.

A method of generating a data output by latching a data input based on a clock input, the method comprising:

• generating, based on the data input, a first data signal;
• generating, based on the clock input and the first data signal, a second data signal complementary to the first data signal and a clock signal complementary to the clock input;
• and
• generating the data output by latching a third data signal based on the clock input, the second data signal, and the clock signal, wherein the third data signal is complementary to the second data signal,
• wherein generating the second data signal and the clock signal comprises floating, based on the first data signal and the third data signal, a first node, and wherein the clock signal is generated at the first node.