Semiconductor package and method of manufacturing semiconductor package

A semiconductor package comprising:

• a substrate including a plurality of bonding pads;
• a plurality of semiconductor chips stacked on the substrate in a vertical direction perpendicular to an upper surface of the substrate, each semiconductor chip of the plurality of semiconductor chips having a rear surface facing the substrate, a front surface opposite to the rear surface, and a plurality of side surfaces connecting the front surface to the rear surface;
• a plurality of attachment films, each attachment film being disposed on a rear surface of a corresponding semiconductor chip of the plurality of semiconductor chips;
• and
• a plurality of connection members electrically connecting the plurality of semiconductor chips and the plurality of bonding pads of the substrate with each other;
• wherein each of the plurality of semiconductor chips includes:
• a plurality of connection pads adjacent to a first edge of the front surface;
• and
• a passivation layer disposed on the front surface, the passivation layer exposing at least a portion of each connection pad of the plurality of connection pads, and
• wherein each connection member of at least some connection members, among the plurality of connection members, includes:
• a plurality of insulating patterns on one side surface, among the plurality of side surfaces of each of the plurality of semiconductor chips, that is connected to the first edge;
• and
• a plurality of conductive patterns extending from the plurality of connection pads of each semiconductor chip of the plurality of semiconductor chips onto the plurality of insulating patterns, the plurality of conductive patterns electrically connected to the plurality of bonding pads.

A semiconductor package comprising:

• a substrate including a plurality of bonding pads;
• a plurality of semiconductor chips stacked on the substrate in a vertical direction perpendicular to an upper surface of the substrate, each semiconductor chip of the plurality of semiconductor chips having a rear surface facing the substrate, a front surface opposite to the rear surface, and a plurality of side surfaces connecting the front surface to the rear surface;
• and
• a plurality of connection members electrically connecting the plurality of semiconductor chips and the plurality of bonding pads of the substrate with each other;
• wherein each semiconductor chip of the plurality of semiconductor chips includes:
• a plurality of connection pads adjacent to a first edge of the front surface;
• a passivation layer disposed on the front surface, the passivation layer exposing at least a portion of each connection pad of the plurality of connection pads;
• and
• a conductive dummy pattern disposed at the front surface and a first side surface among the plurality of side surfaces, the first side surface being connected to the first edge of the front surface, and
• wherein the plurality of connection members include a first group of connection members, each connection member of the first group of connection members including:
• an insulating pattern covering the conductive dummy pattern on the first side surface and the front surface of a corresponding semiconductor chip of the plurality of semiconductor chips;
• and
• a conductive pattern extending from a corresponding connection pad of each semiconductor chip of the plurality of semiconductor chips onto the insulating pattern, the conductive pattern electrically connected to a corresponding one of the plurality of bonding pads.