Non-volatile memory device

A nonvolatile memory device comprising:

• a peripheral circuit comprising a substrate;
• a memory cell array on the peripheral circuit;
• wherein the peripheral circuit comprises a first transistor and a second transistor spaced apart from each other and on an active region defined by a device isolation film on the substrate,
• wherein the first transistor comprises:
• a first gate structure on the active region;
• a first offset spacer extending in a first direction parallel to an upper surface of the substrate on an upper surface of the active region and extending in a second direction perpendicular to the first direction on a sidewall of the first gate structure;
• and
• a first gate spacer on a sidewall of the first offset spacer,
• wherein the second transistor comprises:
• a gate dielectric layer on the active region;
• a second gate structure on the gate dielectric layer;
• a second offset spacer extending in the first direction on an upper surface of the gate dielectric layer and extending in the second direction on a sidewall of the second gate structure;
• a third offset spacer between the second offset spacer and the second gate structure, between the second offset spacer and the gate dielectric layer;
• a second gate spacer on a sidewall of the second offset spacer opposite the sidewall of the first offset spacer in the first direction;
• and
• an interface film between the second offset spacer and the third offset spacer,
• wherein the first offset spacer and the second offset spacer extend conformally.

A nonvolatile memory device comprising:

• a peripheral circuit comprising a plurality of transistors on a substrate;
• and
• a memory cell array controlled by the peripheral circuit,
• wherein the plurality of transistors comprise a first transistor and a second transistor,
• wherein the first transistor and the second transistor each comprise a first gate structure and a second gate structure extending in a first direction parallel to the substrate and on an active region defined by a device isolation film on the substrate, wherein the first gate structure and second gate structure are spaced apart from each other in a second direction intersecting the first direction,
• wherein the first gate structure and the second gate structure each comprise an electrode layer comprising a polysilicon electrode and a gate capping pattern on the electrode layer,
• wherein the first transistor comprises a first offset spacer extending along a sidewall of the first gate structure in a third direction perpendicular to the first direction and the second direction and extending along an upper surface of the active region in the second direction, and a gate spacer on a sidewall of the first offset spacer,
• wherein the second transistor comprises a second offset spacer having a second thickness in a range of 10 Å to 70 Å, extending along a sidewall of the second gate structure in the third direction, and extending along an upper surface of the active region in the second direction, a third offset spacer on the second offset spacer, and a gate spacer on the third offset spacer,
• wherein a first thickness of the first offset spacer and a third thickness of the third offset spacer are in the range of 10 Å to 70 Å and the first offset spacer and the third offset spacer extend conformally,
• wherein an interface film is between the third offset spacer and the second offset spacer, and
• wherein a residual offset spacer is between the first offset spacer and a sidewall and an upper surface of the gate capping pattern in the first gate structure.