Sensor Event Generation Circuit

A sensor event generation circuit, comprising:

• a first sensor circuit arranged to provide a first electrical analog signal, and a first switch connected to the first sensor circuit and arranged to receive the first electrical analog signal,
• a second sensor circuit arranged to provide a second electrical analog signal, and a second switch connected to the second sensor circuit and arranged to receive the second electrical analog signal, and
• a selection control circuit arranged to control the operation of the first switch and the second switch so that only one of the first and second switches can be in a closed state at a time,
• wherein the sensor event generation circuit comprises:
• a state value digital memory having a first digital state memory for storing a first digital state value and a second digital state memory for storing a second digital state value, wherein the selection control circuit is arranged to control the state value digital memory to select the first digital state memory when the first switch is in the closed state or the second digital state memory when the second switch is in the closed state,
• a digital-to-analog converter connected to the state value digital memory and arranged to receive the digital state value stored in the selected digital state memory and to convert the digital state value to a previous state analog value,
• an analog-to-digital converter connected to the first switch, the second switch and the digital-to-analog converter and arranged to receive the previous state analog value and one of the electrical analog signals and to convert the difference of the electrical analog signal and the previous state analog value to a difference digital value,
• an event indication circuit connected to the analog-to-digital converter and arranged to receive the difference digital value and to determine whether the difference digital value is above a positive threshold and in such case assert a positive event indication signal, and to determine whether the difference digital value is below a negative threshold and in such case assert a negative event indication signal,
• an event presence circuit connected to the event indication circuit and arranged to assert an event presence signal if either the positive event indication signal or the negative event indication signal has been received, and
• a summing circuit connected to the analog-to-digital circuit and the state value digital memory and arranged to receive the difference digital value and the digital state value stored in the selected digital state memory, to sum the difference digital value with the digital state value and to produce a summing result, wherein the summing result is arranged to be written to the selected digital state memory if the event presence signal has been asserted.