Two-way transceiver encoding for simultaneous bidirectional signaling

A die-to-die communication interface comprising:

• a first die comprising a first processing core having first control logic and a first plurality of transceivers coupled to the first control logic;
• a second die comprising a second processing core having second control logic and a second plurality of transceivers coupled to the second control logic, wherein the first and second plurality of transceivers are simultaneous bidirectional transceivers;
• a plurality of data lanes communicatively coupling the first plurality of transceivers to the second plurality of transceivers;
• and
• wherein the first control logic and the second control logic are configured to invert bits transmitted by selected transceivers according to a bit inversion encoding that causes an average current consumption during idle mode to equal an average current consumption during active mode.

A graphics processing unit (GPU) comprising:

• a processing core comprising control logic;
• and
• a plurality of transceivers coupled to the control logic, wherein the plurality of transceivers are simultaneous bidirectional transceivers for communication with a second plurality of transceivers of a second integrated circuit over a plurality of data lanes;
• wherein the control logic is configured to invert bits transmitted by a subset of the plurality of transceivers according to a sequential indexing scheme that maintains equal average current consumption during idle mode and active mode.