Semiconductor device including daisy-chained delay cells and method of forming the same

A semiconductor device comprising:

• a first row of transistors that includes, in a sequence from a first end to a second end of the first row, at least a first dummy group, a first delay cell, a second delay cell, and a second dummy group, wherein:
• the first dummy group includes one or more non-operational transistors,
• the second dummy group includes one or more non-operational transistors,
• the first delay cell includes active transistors configured as:
• a basic inverter configured to output a first inverted signal in response to receiving a first input signal, and
• a float-resistant inverter configured to output a second inverted signal in response to receiving the first inverted signal,
• the second delay cell includes active transistors configured as at least one inverter, and
• the first row is free of non-operational transistors between the first delay cell and the second delay cell.

A method of forming a semiconductor device, the method comprising:

• forming a first dummy group that includes at least a first non-operational transistor;
• forming a second dummy group that includes at least a second non-operational transistor;
• forming a first delay cell in which:
• a basic inverter is configured to receive an input signal at a first node and output a first inverted signal at a second node, the first node representing an input node of the basic inverter, and
• a float-resistant inverter is configured to receive the first inverted signal at the second node and output a second inverted signal at a third node;
• and
• forming a second delay cell,
• wherein the first and second dummy groups and the first and second delay cells are formed in a first row in which at least the first delay cell and the second delay cell are arranged between first dummy group and the second dummy group, and the first and second delay cells are free from having another dummy group therebetween.