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US 2026/0188404 A1Published application
Memory test algorithms for 3d integrated circuits (ic)
AssigneeIntel Corporation
InventorsRakesh KANDULA, Savitha SWAMY
Life of this patent
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Abstract
Devices and methods for testing interconnect lanes of multichip packages with memory test algorithms are provided. The multichip packages that can be tested can comprise a plurality of semiconductor dies mounted on an active interposer.
Claims17
An assembly comprising:
- at least two semiconductor dies wherein a first semiconductor die of the at least two semiconductor dies includes signal transmission circuitry, wherein the first semiconductor die includes first test circuitry that includes a pattern generator, wherein a second semiconductor die of the at least two semiconductor dies includes receive circuitry and second test circuitry, and wherein the second test circuitry includes a comparator;
- a first interconnect lane that electrically connects the first semiconductor die with the second semiconductor die of the at least two semiconductor dies, wherein the first test circuitry is capable of assigning an address to the first interconnect lane;
- and
- a second interconnect lane that is capable of sending a signal from the first test circuitry to the second test circuitry indicating that a test sequence is done.
1 more element
A method comprising:
- selecting a multichip package for testing, wherein the multichip package comprises first interconnect lanes that electrically connect a first semiconductor die of the multichip package with a second semiconductor die of the multichip package;
- selecting a memory test algorithm to test viability of the first interconnect lanes;
- running the memory test algorithm to test viability of the first interconnect lanes, and
- determining viability of the first interconnect lanes.
1 more element
At least one machine-readable storage medium comprising non-transitory instructions, that when executed by a processor, cause a device to:
- select a memory test algorithm to test viability of interconnect lanes of a multichip package wherein the interconnect lanes electrically connect a first semiconductor die of the multichip package with a second semiconductor die of the multichip package;
- run the memory test algorithm to test viability of the interconnect lanes;
- and
- determine viability of the interconnect lanes based on results of the memory test algorithm.
1 more element
Dependencies are inferred from the claim text.