Bit cell, in-memory computing circuit for majority functions, and in-memory computing method

An in-memory computing circuit comprising:

• an array of bit cells in columns and rows;
• first word lines for the rows, respectively;
• and
• second word lines for the rows, respectively, wherein each bit cell includes:
• a variable resistor and a first transistor connected in series between a first end node and a second end node, wherein a first gate of the first transistor is connected to a first word line for a row;
• and
• a second transistor connected between the first end node and the second end node, wherein a second gate of the second transistor is connected to a second word line for the row.

An in-memory computing method comprising:

• storing bit values in bit cells of an array of the bit cells arranged in columns and rows,
• wherein each bit cell includes:
• a variable resistor and a first transistor connected in series between a first end node and a second end node, wherein a first gate of the first transistor is connected to a first word line for a row;
• and
• a second transistor connected between the first end node and the second end node, wherein a second gate of the second transistor is connected to a second word line for the row, and
• wherein the bit cells in the columns are connected in series forming bit cell stacks;
• and
• performing a read operation to concurrently compute majority functions directed to stored bit values in selected rows of the bit cell stacks.