Multi-chip package and memory system

A memory system comprising:

• a multi-chip package;
• and
• a memory controller configured to control the multi-chip package through a signal transmission line,
• wherein the multi-chip package comprises:
• a printed circuit board (PCB) extending in a first direction and a second direction, wherein the second direction crosses the first direction;
• and
• a plurality of memory chips stacked on the PCB in a third direction,
• wherein the plurality of memory chips are configured to communicate with the memory controller through the signal transmission line and to share the signal transmission line,
• wherein the third direction is perpendicular to the first direction and the second direction,
• wherein each of the plurality of memory chips comprises a respective one of a plurality of on-die termination (ODT) circuits coupled to the signal transmission line, and
• wherein each of the plurality of memory chips is configured to individually set a resistance value of the respective one of the plurality of ODT circuits based on respective position information of the respective memory chip relative to a surface of the PCB.

A memory system comprising:

• a memory controller comprising a central processing unit (CPU), wherein the memory controller is mounted on a printed circuit board (PCB) extending in a first direction and a second direction crossing the first direction;
• a first memory module comprising a first group of memory chips, wherein the first memory module is mounted in a first socket on the PCB, the first socket being spaced apart from the memory controller by a first distance in the first direction;
• and
• a second memory module comprising a second group of memory chips, wherein the second memory module is mounted in a second socket on the PCB, the second socket being spaced apart from the memory controller by a second distance in the first direction,
• wherein a first memory chip among the first group of memory chips and a second memory chip among the second group of memory chips communicate with the memory controller through a signal transmission line and share the signal transmission line, and each of the first memory chip and the second memory chip comprises an on-die termination (ODT) circuit coupled to the signal transmission line,
• wherein the first memory chip is configured to set a resistance value of the ODT circuit of the first memory chip based on position information of the first memory chip associated with a distance of the first memory chip from the memory controller in the first direction, and
• wherein the second memory chip is configured to set a resistance value of the ODT circuit of the second memory chip based on position information of the second memory chip associated with a distance of the second memory chip from the memory controller in the first direction.