Cooperative parallel memory allocation
AssigneeNVIDIA Corporation
InventorHarold Carter Edwards
Life of this patent
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AssigneeNVIDIA Corporation
InventorHarold Carter Edwards
Estimating the term…
Apparatuses, systems, and techniques to perform multi-threaded processing in parallel by one or more software programs on a parallel processing unit (PPU), such as a graphics processing unit (GPU), or any other processing unit capable of supporting multi-threaded software execution. In at least one embodiment, processors, systems, and techniques, during execution of two or more software threads in parallel, identify, using at least one software thread of the two or more software threads, a child node of a parent node in a shared hierarchical data structure stored in memory as a candidate for a state-modifying operation, lock the parent node of the child node to indicate that an operation involving the child node is in progress, and perform, by the at least one software thread, a state-modifying operation on data associated with the child node when the parent node is locked.
One or more processors, comprising:
A system, comprising:
A method, comprising:
Dependencies are inferred from the claim text.