Code vectorization method and apparatus

An electronic device, comprising:

• one or more processors and a memory, wherein the one or more processor and the memory are connected to each other;
• the memory is configured to store one or more programs;
• and
• when the one or more programs are executed by the one or more processors, the one or more processors are caused to:
• obtain attribute information of multidimensional loop code, wherein the multidimensional loop code comprises a plurality of pieces of single-level loop code, and each piece of single-level loop code in the plurality of pieces of single-level loop code is used to implement one level of loop in a multi-level loop;
• determine, based on the attribute information, a hardware logic level corresponding to each level of target loop code in the multidimensional loop code, wherein each level of target loop code is a piece of single-level loop code to be vectorized in the plurality of pieces of single-level loop code, the plurality of hardware logic levels indicate a multi-level memory access rule of a vector computing unit, and each hardware logic level corresponds to a rule for one level of memory access in the multi-level memory access rule;
• split each level of target loop code based on a length upper limit of the hardware logic level corresponding to the level of target loop code to obtain a plurality of code blocks, and combining the plurality of code blocks into a plurality of pieces of multidimensional subloop code based on a level relationship between hardware logic levels corresponding to the plurality of code blocks;
• and
• update the multidimensional loop code to a vector instruction based on the plurality of pieces of multidimensional subloop code and the attribute information, wherein the vector instruction is used by the vector computing unit to perform vector computing.

A non-transitory computer-readable storage medium, comprising a computer program, wherein when the computer program is run on an electronic device, the electronic device is caused to:

• obtain attribute information of multidimensional loop code, wherein the multidimensional loop code comprises a plurality of pieces of single-level loop code, and each piece of single-level loop code in the plurality of pieces of single-level loop code is used to implement one level of loop in a multi-level loop;
• determine, based on the attribute information, a hardware logic level corresponding to each level of target loop code in the multidimensional loop code, wherein each level of target loop code is a piece of single-level loop code to be vectorized in the plurality of pieces of single-level loop code, the plurality of hardware logic levels indicate a multi-level memory access rule of a vector computing unit, and each hardware logic level corresponds to a rule for one level of memory access in the multi-level memory access rule;
• split each level of target loop code based on a length upper limit of the hardware logic level corresponding to the level of target loop code to obtain a plurality of code blocks, and combining the plurality of code blocks into a plurality of pieces of multidimensional subloop code based on a level relationship between hardware logic levels corresponding to the plurality of code blocks;
• and
• update the multidimensional loop code to a vector instruction based on the plurality of pieces of multidimensional subloop code and the attribute information, wherein the vector instruction is used by the vector computing unit to perform vector computing.

A chip, comprising one or more interface circuits and one or more processors, wherein the interface circuit is configured to:

• receive a signal from a memory of an electronic device, and send the signal to the processor, and the signal comprises computer instructions stored in the memory;
• and when the processor executes the computer instructions, the electronic device is caused to:
• obtain attribute information of multidimensional loop code, wherein the multidimensional loop code comprises a plurality of pieces of single-level loop code, and each piece of single-level loop code in the plurality of pieces of single-level loop code is used to implement one level of loop in a multi-level loop;
• determine, based on the attribute information, a hardware logic level corresponding to each level of target loop code in the multidimensional loop code, wherein each level of target loop code is a piece of single-level loop code to be vectorized in the plurality of pieces of single-level loop code, the plurality of hardware logic levels indicate a multi-level memory access rule of a vector computing unit, and each hardware logic level corresponds to a rule for one level of memory access in the multi-level memory access rule;
• split each level of target loop code based on a length upper limit of the hardware logic level corresponding to the level of target loop code to obtain a plurality of code blocks, and combining the plurality of code blocks into a plurality of pieces of multidimensional subloop code based on a level relationship between hardware logic levels corresponding to the plurality of code blocks;
• and
• update the multidimensional loop code to a vector instruction based on the plurality of pieces of multidimensional subloop code and the attribute information, wherein the vector instruction is used by the vector computing unit to perform vector computing.