Scan chain control
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJia Han LIN, Shih-Chang TSAI, Feng-Ming KUO, Chung-Sheng YUAN, Chung-Hsing WANG, Yi-Kan CHENG
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure are directed to scan chain systems and methods for inputting repeated sequences of bits to a sequence of flip flops that include multi-bit flip flops and single bit flip flops. One example includes a control circuit that includes a bit counter, a multiplexer, a first group control circuit, and a second group control circuit.
Claims20
A control circuit for loading a repeated sequence to a plurality of flip flops, the control circuit comprising:
- a bit counter configured to output a first bit and a second bit based on a first control signal;
- a plurality of multiplexers configured to receive the first bit and the second bit as input and output a sequence of bits;
- and
- a plurality of group control circuits configured to receive the sequence of bits as input and output a plurality of first group control signals, the plurality of first group control signals each including a noninverted signal and an inverted signal.
A scan chain circuit, comprising:
- a plurality of flip flops, the plurality of flip flops including single bit flip flops and multi-bit flip flops and are in a predetermined output to input sequence;
- a plurality of input circuits coupled to the plurality of flip flops;
- and
- a control circuit comprising:
- a bit counter configured to output a first bit and a second bit based on a first control signal;
- a plurality of multiplexers configured to receive the first bit and the second bit as input and output a sequence of bits;
- and
- plurality of group control circuits configured to receive the sequence of bits as input and output a plurality of first group control signals;
- wherein each of the plurality of group control circuits are coupled to a corresponding input circuit of the plurality of input circuits.
A method, comprising:
- receiving, by a control circuit, one or more input signals and a scan clock signal;
- generating, by a bit counter of the control circuit, a plurality of input bits, wherein the plurality of input bits includes a repeated sequence of bits and offsets of the repeated sequence of bits;
- generating, by group control circuits of the control circuit, a plurality of group control signals based on the plurality of input bits;
- providing, by the control circuit, each group control signal to a corresponding group of flip-flops that form a plurality of flip-flops;
- and
- detecting an output of each of the corresponding group of flip-flops.
Dependencies are inferred from the claim text.