Back to results
US 2026/0181849 A1Published application
Memory architectures with backside metal zero (bm0) bit-lines
AssigneeIntel Corporation
InventorsJohn Reginald Riley, Mauro J. Kobrinsky, Seenivasan Subramaniam, Anandkumar Mahadevan Pillai, Fatih Hamzaoglu, Zheng Guo
Life of this patent
Estimating the term…
Abstract
Memory architectures with backside metal zero (M0) bit-lines. SRAM bit-cells with the memory bit-lines traversing the memory bank in backside metal zero (BM0), rather than M0 or another metal layer in the metal stack. BM0 bit-lines have a larger width and pitch than M0, resulting in a reduced resistance and capacitance on the bit-lines.
Claims20
An apparatus, comprising:
- a substrate comprising an upper surface and a lower surface;
- a static random access (SRAM) memory cell located between the upper surface and the lower surface;
- the SRAM memory cell comprising a first conductive via that extends from a first region of n-type diffusion to the lower surface and a second conductive via that extends from a second region of n-type diffusion to the lower surface;
- the lower surface comprising a first conductive trace and a second conductive trace, arranged at a pitch;
- the first conductive trace and the second conductive trace comprising a conductive material with a width equal to at least 20 nanometers;
- the first conductive trace electrically coupled to the first conductive via;
- and
- the second conductive trace electrically coupled to the second conductive via.
5 more elements
A package assembly, comprising:
- a die having an upper surface and a backside;
- a static random-access memory (SRAM) component positioned between the upper surface and the backside and comprising a plurality of SRAM memory cells;
- and
- the SRAM component further comprising periphery circuitry with a sense amp;
- wherein individual SRAM memory cells comprise:
- a first conductive via extending from a first region of n-type diffusion to the backside and a second conductive via extending from a second region of n-type diffusion to the backside;
- a first conductive trace on the backside to electrically couple the first conductive via to the sense amp;
- and
- a second conductive trace on the backside to electrically couple the second conductive via to the sense amp;
- wherein the first conductive trace and the second conductive trace comprise a width of 24 nanometers +/−2 nanometers.
7 more elements
A method, comprising:
- fabricating a static random-access memory (SRAM) cell on a substrate having an upper surface and a backside;
- creating a first via to electrically couple a bit-line output to the backside;
- creating a second via to electrically couple a bit-line-bar output to the backside;
- electrically coupling the first via to a first conductive trace in a backside metal zero (BM0) layer in the substrate;
- electrically coupling the first via to a second conductive trace in the BM0 layer;
- and
- wherein the first conductive trace and second conductive trace are 24 nanometers wide +/−2 nanometers.
4 more elements
Dependencies are inferred from the claim text.