Semiconductor device, control circuit, control method, and storage medium

A control circuit,

• the control circuit being electrically connected to a connection point between a first source terminal of a first semiconductor element and a second source terminal of a second semiconductor element,
• the first semiconductor element being normally-on,
• the second semiconductor element being a p-type MOSFET,
• the control circuit being configured to:
• apply a first voltage to the connection point when a potential of the second source terminal is not less than a potential of a second drain terminal of the second semiconductor element;
• and
• apply a second voltage to the connection point when the potential of the second source terminal is less than the potential of the second drain terminal,
• the second voltage being less than the first voltage,
• an absolute value of a difference between the second voltage and a voltage applied to a second gate terminal of the second semiconductor element being greater than an absolute value of a threshold voltage of the second semiconductor element.

A control method of a semiconductor device,

• the semiconductor device including:
• a first semiconductor element including a first source terminal and a first drain terminal, the first semiconductor element being normally-on;
• and
• a second semiconductor element including a second source terminal and a second drain terminal, the second source terminal being electrically connected to the first source terminal, the second semiconductor element being a p-type MOSFET,
• the control method comprising:
• applying a first voltage to a connection point between the first source terminal and the second source terminal when a potential of the second source terminal is not less than a potential of the second drain terminal;
• and
• applying a second voltage to the connection point when the potential of the second source terminal is less than the potential of the second drain terminal,
• the second voltage being less than the first voltage,
• an absolute value of a difference between the second voltage and a voltage applied to a second gate terminal of the second semiconductor element being greater than an absolute value of a threshold voltage of the second semiconductor element.