Discrete cosine transform processing device and discrete cosine transform processing method

Abstract

A discrete cosine transform processing device includes an adder, a register, multiple multiply-accumulate operation circuits, an accumulator, an operation control circuit and an output circuit. The adder processes first input data based on a first permutation matrix to generate second input data. The register stores an operation matrix. The operation control circuit configures the multiply-accumulate operation circuits and the accumulator based on a matrix multiplication operation corresponding to a unit dimension, such that the operation matrix and the second input data are multiplied and accumulated by the multiply-accumulate operation circuits and the accumulator to generate a first operation result. The output circuit processes the first operation result based on a second permutation matrix to generate a second operation result, wherein the first permutation matrix, the operation matrix, and the second permutation matrix are derived from decomposition of a discrete cosine transform matrix.

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