Input hold for dual power rail memories
AssigneeQUALCOMM Incorporated
InventorsSonia GHOSH, Xiao CHEN
Life of this patent
Estimating the term…
Abstract
A data capture circuit has a first latch provided in a first voltage domain and a gating circuit also provided in the first voltage domain. The gating circuit may be configured to couple an input signal to an input of the first latch when a first clock signal is in a first signaling state and a second clock signal is in a second signaling state. The gating circuit may be disabled when the first clock signal is in a third signaling state or the second clock signal is in a fourth signaling state. The first clock signal may be configured to control timing of circuits in the first voltage domain and the second clock signal may be configured to control timing of circuits in a second voltage domain.
Claims20
A data capture circuit, comprising:
- a first latch provided in a first voltage domain;
- and
- a gating circuit provided in the first voltage domain and configured to couple an input signal to an input of the first latch when a first clock signal is in a first signaling state and a second clock signal is in a second signaling state,
- wherein the gating circuit is disabled when the first clock signal is in a third signaling state or the second clock signal is in a fourth signaling state, and
- wherein the first clock signal is configured to control timing of circuits in the first voltage domain and the second clock signal is configured to control timing of circuits in a second voltage domain.
An apparatus comprising:
- means for gating an input signal in a first voltage domain, the input signal being a level-shifted version of a control or data signal generated by a circuit in a second voltage domain;
- and
- means for capturing signaling state of the input signal in the first voltage domain, including a first latch that is controlled by a first clock signal and a second clock signal,
- wherein the means for gating the input signal is configured to couple the input signal to an input of the first latch when the first clock signal is in a first signaling state and the second clock signal is in a second signaling state, and
- wherein the first clock signal is configured to control timing of circuits in the first voltage domain and the second clock signal is configured to control timing of circuits in the second voltage domain.
A method for transferring data between voltage domains, comprising:
- receiving an input signal in a first voltage domain, the input signal being a level-shifted version of a control or data signal generated by a circuit in a second voltage domain;
- coupling the input signal to an input of a first latch in the first voltage domain when a first clock signal is in a first signaling state and a second clock signal is in a second signaling state;
- and
- blocking the input signal from the input of the first latch when the first clock signal is in a third signaling state or the second clock signal is in a fourth signaling state, wherein the first clock signal is configured to control timing of circuits in the first voltage domain and the second clock signal is configured to control timing of circuits in the second voltage domain.
Dependencies are inferred from the claim text.