Method of and system for generating layout diagram of integrated circuit device having transistor architecture

A system for manufacturing an integrated circuit (IC) device, the system comprising a processor and a non-transitory computer readable storage medium including computer program code for one or more programs, the non-transitory computer readable storage medium, the computer program code and the processor being configured to cause the system at least to perform operations comprising:

• receiving an layout diagram of an IC device, the layout diagram including as follows,
• a gate region having a first width across a first isolation region, an active region, and a second isolation region,
• a first gate via at a first location along a second width across the active region, and
• a second gate via at a first edge of the gate region;
• building a gate-resistance compact network, which includes at least four nodes of a three-dimensional transistor architecture represented by the layout diagram and at least five equivalent resistances between corresponding ones of the at least four nodes;
• determining an effective resistance of the gate region based on the equivalent resistances in the gate-resistance compact network;
• and
• performing a circuit simulation based on the effective resistance.

A non-transitory computer-readable medium having stored thereon computer executable instructions representing a method of generating an integrated circuit (IC) layout diagram of an IC device, the computer executable instructions being executable by at least one processor to perform the method including:

• receiving the layout diagram of the IC device, the layout diagram including as follows,
• a gate region having a first width across an active region, and
• a first gate via, at a first location along the first width,
• selecting at least four nodes and a gate structure of the IC device;
• modeling the gate region using a gate-resistance compact network, including the at least four nodes and at least five equivalent resistances correspondingly between each two ones of the nodes of the at least four nodes;
• and
• determining compliance of the layout diagram with a design specification based on the gate-resistance compact network.