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US 2026/0169932 A1Published application
Gray coding mechanism to reduce metal usage
AssigneeNVIDIA Corporation
InventorsLei Wang, Chen Lu, Zhenye Jiang, Haiyan Gong, Hwong-Kwo Lin
Life of this patent
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Abstract
Metal track reduction mechanisms in systems utilizing an address bus wherein an address decoder is configured to operate on a first subset of applied address bits and a Gray Coder is configured to operate on a second subset of the applied address bits to generate a Gray Code. A sequence of inverters is configured to invert a bit of the Gray Code at multiple locations along the address bus, each location corresponding to a component to select with the applied address.
Claims20
A machine memory comprising:
- an address bus;
- an address decoder configured to operate on a first subset of applied address bits;
- a Gray Coder configured to operate on a second subset of the applied address bits to generate a Gray Code;
- and
- a sequence of inverters configured to invert a bit of the Gray Code at multiple locations along the address bus, each location corresponding to a data path input-output stage (DPIO).
2 more elements
A system comprising:
- a bus;
- a decoder configured to generate a first subset of selection bits on the bus;
- a Gray Coder configured to generate a Gray Code on the bus;
- and
- a sequence of inverters configured to invert a single bit of the Gray Code at each of a plurality of locations along the bus, each location corresponding to a component to select for an operation.
2 more elements
A method comprising:
- operating a decoder to generate a first subset of selection bits on a bus;
- operating a Gray Coder to generate a Gray Code on the bus;
- and
- propagating the Gray Code through a sequence of inverters such that a single bit of the Gray Code in inverted at each of a plurality of locations along the bus, each location corresponding to a component to select for an operation.
1 more element
Dependencies are inferred from the claim text.