Floating-point operand multiplier using decomposition of operands into lower-precision floating-point numbers

A decomposition circuit of an incoming binary number for a binary arithmetic operator, the incoming number having a floating-point format with an exponent and a fractional mantissa, and implementing subnormal numbers with an implicit mantissa bit, the decomposition circuit being hardwired to:

• decompose the incoming number into a pair of high and low components in an internal format of lower precision than the format of the incoming number, with an exponent having at least the number of bits of the exponent of the incoming number plus 1 and a significand having a number of bits at least equal to half the number of bits of the fractional mantissa plus 1;
• directly connect the bits of the significand of the high component respectively to a circuit providing a value of the implicit bit and to the most significant bits of the fractional mantissa;
• directly connect the bits of the significand of the low component respectively to the remaining bits of the fractional mantissa;
• assign to the exponent of the high component the exponent of the incoming number increased by a size of the significands of the components;
• and
• assign to the exponent of the low component an unchanged exponent of the incoming number.