Group iii-v power semiconductor device and method of manufacturing same

A group III-V power semiconductor device comprising:

• a substrate;
• a channel layer on the substrate;
• a barrier layer on the channel layer;
• a single layer comprising a capping layer and one or more low-resistance regions, along a first direction;
• a gate electrode on the capping layer,
• a source electrode and a drain electrode that are spaced from each other with the gate electrode therebetween;
• and
• a hole injection region in the single layer, between the capping layer and the drain electrode,
• wherein the low-resistance region is between the capping layer and the drain electrode.

A method of manufacturing a group III-V power semiconductor device, the method comprising:

• sequentially forming a buffer layer, a channel layer, and a barrier layer on a substrate;
• forming a doped layer doped with a first conductivity type on the barrier layer;
• forming a capping layer and a low-resistance region in the doped layer;
• forming a source electrode and a drain electrode that are spaced from each other on the barrier layer, and
• forming a gate electrode on the capping layer, wherein the low-resistance region has a lower resistance than the capping layer.