Interface with increased error correction capability

An interface configured to reduce the impact of power fluctuations on data transmissions, the interface comprising:

• F forward error correction (FEC) encoders, where F is an integer greater than one;
• a transmit (Tx) FEC mapping module configured to:
• receive Q bits corresponding to an info-message on a parallel input bus;
• and
• map the Q bits to D data portions each corresponding to one of the F FEC encoders, S slices, and B time slots for time division multiplexing (TDM), where Q, D, S, and B are integers greater than one;
• wherein each of the F FEC encoders is configured to generate P/F FEC parity bits for D/F data portions, where P is an integer greater than one;
• S Tx parallel registers corresponding to the S slices, respectively;
• and
• S sets of L lanes,
• wherein each of the S Tx parallel registers is connected to one of the S sets of L lanes and is configured to transmit D/S data portions and P/S FEC parity bits over a communications channel using TDM and the B time slots.