Asynchronous sar logic

A circuit for detecting metastability in an asynchronous successive approximation register analogue to digital converter;

• the circuit comprising:
• a two-output comparator;
• control logic;
• a first output terminal;
• and
• a second output terminal;
• wherein the two-output comparator is arranged to receive first and second input signals;
• wherein the two-output comparator is arranged to:
• receive a trigger signal from the control logic;
• based on the receipt of the trigger signal:
• set a first comparison signal and a second comparison signal to a reset state;
• compare the first input signal with the second input signal;
• and
• drive one of the first and second comparison signals to a set state based on the comparison;
• wherein the control logic is configured such that:
• the first output terminal is in a set state when the first comparison signal is in a set state;
• the second output terminal is in a set state when the second comparison signal is in a set state;
• and
• if a predetermined duration passes after the start of the comparison by the two-output comparator and if the first comparison signal and the second comparison signal are both in the reset state, the control logic outputs a set state at both the first output terminal and the second output terminal.