Memory with Serialized Redundancy Interface
AssigneeQUALCOMM Incorporated
InventorsChulmin JUNG, Dhvani SHETH, Seohee KIM, Anil Chowdary KOTA
Life of this patent
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Abstract
A memory is provided having a plurality of banks. A shared redundancy address decoder decodes a redundancy address for each of the banks to provide a decoded redundancy address to each bank. A serializer serializes the decoded redundancy address into a serialized decoded redundancy address. The banks deserialize the serialized decoded redundancy address to recover their decoded redundancy address. Should one of the banks have a defect, the bank repairs the defect by reconfiguring its resources responsive to its decoded redundancy address.
Claims20
A memory, comprising:
- a redundancy address decoder configured to decode a first redundancy address into a first decoded redundancy address;
- a serializer configured to serialize the first decoded redundancy address into a first serialized decoded redundancy address;
- and
- a first bank configured to deserialize the first serialized decoded redundancy address to recover the first decoded redundancy address.
A memory redundancy method, comprising:
- decoding a first redundancy address into a first decoded redundancy address;
- serializing the first decoded redundancy address into a first serialized decoded redundancy address;
- deserializing the first serialized decoded redundancy address to recover the first decoded redundancy address in a first bank;
- and
- repairing a defect in the first bank responsive to the first decoded redundancy address.
A memory, comprising:
- a serializer configured to serialize a first decoded redundancy address into a first serialized decoded redundancy address and configured to serialize a second decoded redundancy address into a second serialized decoded redundancy address;
- a first bank configured to deserialize the first serialized decoded redundancy address to recover the first decoded redundancy address, the first bank being further configured to repair a defect responsive to the first decoded redundancy address;
- and
- a second bank configured to deserialize the second serialized decoded redundancy address to recover the second decoded redundancy address, the second bank being further configured to repair a defect responsive to the second decoded redundancy address.
Dependencies are inferred from the claim text.