Three-state programming of memory cells

An apparatus, comprising:

• a memory having a plurality of memory cells;
• and
• circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by:
• applying a voltage pulse having a first polarity to the memory cell;
• and
• applying an additional voltage pulse to the memory cell without determining whether the memory cell snaps back in response to the applied voltage pulse, wherein the additional voltage pulse has a second polarity that is opposite the first polarity.

A method of operating memory, comprising:

• programming a memory cell to one of three possible data states by:
• applying a voltage pulse having a first polarity to the memory cell;
• and
• applying a plurality of additional voltage pulses to the memory cell without determining whether the memory cell snaps back in response to the applied voltage pulse, wherein at least one of the additional voltage pulses has a second polarity that is opposite the first polarity.