Apparatus And Method For Memory Alias Disambiguation Training
AssigneeIntel Corporation
InventorsSudeepto MAJUMDAR, Mark DECHENE, Michael MEEUWSEN, Meenakshi MARATHE, Brendan WEST
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AssigneeIntel Corporation
InventorsSudeepto MAJUMDAR, Mark DECHENE, Michael MEEUWSEN, Meenakshi MARATHE, Brendan WEST
Estimating the term…
Embodiments of a processor for MAD training comprise: decode circuitry to decode instructions into uops, including a plurality of load and store uops; memory execution circuitry executes the plurality of load uops to load data from a memory subsystem and to execute the plurality of store uops to store data to the memory subsystem; and memory alias disambiguation (MAD) prediction circuitry to make a prediction as to whether a first load uop of the plurality of load uops can be executed prior to execution of a first one or more store uops of the plurality of store uops without causing a conflict, the MAD circuitry to make the prediction based on first prediction circuitry when a first confidence value indicated by the first prediction circuitry is above a threshold and to make the prediction based on second prediction circuitry when the first confidence value is at or below the threshold.
A processor, comprising:
A method, comprising:
A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations, comprising:
Dependencies are inferred from the claim text.