Semiconductor devices

A semiconductor device, comprising:

• a substrate;
• a cell structure on a top surface of the substrate;
• and
• a plurality of interconnection layers, which are stacked on the cell structure in a first direction perpendicular to the top surface of the substrate,
• wherein the cell structure comprises a capacitor, the capacitor including
• a plurality of bottom electrodes disposed on the top surface of the substrate and spaced apart from each other in a second direction parallel to the top surface of the substrate,
• a top electrode covering the plurality of bottom electrodes, and
• a dielectric layer between each of the plurality of bottom electrodes and the top electrode,
• wherein an uppermost interconnection layer of the plurality of interconnection layers includes:
• an uppermost interlayer insulating layer,
• uppermost conductive lines horizontally spaced apart from each other on the uppermost interlayer insulating layer, and
• a passivation layer disposed on the uppermost interlayer insulating layer and covering the uppermost conductive lines,
• wherein each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern and an upper metal compound pattern, which are sequentially stacked in the first direction,
• wherein the lower metal compound pattern, the metal pattern and the upper metal compound pattern include a same metallic element, and
• wherein the passivation layer covers top and side surfaces of the uppermost conductive lines.

A semiconductor device, comprising:

• a substrate;
• a capacitor on a top surface of the substrate;
• and
• a plurality of interconnection layers, which are stacked on the capacitor in a first direction perpendicular to the top surface of the substrate,
• wherein the capacitor includes:
• a plurality of bottom electrodes disposed on the top surface of the substrate and spaced apart from each other in a second direction parallel to the top surface of the substrate,
• a top electrode covering the plurality of bottom electrodes, and
• a dielectric layer between each of the plurality of bottom electrodes and the top electrode,
• wherein an uppermost interconnection layer of the plurality of interconnection layers includes:
• an uppermost interlayer insulating layer,
• uppermost conductive lines horizontally spaced apart from each other on the uppermost interlayer insulating layer, and
• a passivation layer disposed on the uppermost interlayer insulating layer and covering the uppermost conductive lines,
• wherein each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern and an upper metal compound pattern, which are sequentially stacked in the first direction,
• wherein the metal pattern is between the lower metal compound pattern and the upper metal compound pattern,
• wherein the metal pattern includes aluminum, and
• wherein the passivation layer covers top and side surfaces of the uppermost conductive lines.