ESD Protection Semiconductor Device

A semiconductor device, comprising

• a well region in a substrate, extending from a top surface of the substrate into the substrate;
• a drain region and a source region in the well region, extending from a top surface of the well region into the well region, wherein the drain region is located at a first end of the well region, the source region is located at a second end of the well region opposite to the first end of the well region, and the drain region is connected to a device to be protected for electrostatic discharge (ESD);
• a gate layer and a field plate layer, disposed on the top surface of the well region between the first end and the second end of the well region and spaced apart, wherein the gate layer is adjacent to the source region, and the field plate layer is adjacent to the drain region;
• a first N+ doped region and a first P+ doped region, located in the well region between the gate layer and the field plate layer, and adjacent to each other;
• a conductive layer covering the source region, the drain region, the gate layer, a portion of the field plate layer, and a portion of the first N+ doped region;
• and
• one or more N+ doped regions and one or more P+ doped regions alternately arranged in the field plate layer, wherein at least one PN junction is formed by the one or more N+ doped regions and the one or more P+ doped regions in the field plate layer.

A semiconductor device, comprising

• a substrate;
• a well region in the substrate, extending from a top surface of the substrate into the substrate;
• a drain region and a source region in the well region, extending from a top surface of the well region into the well region, wherein the drain region is located at a first end of the well region, the source region is located at a second end of the well region opposite to the first end of the well region, the source region is grounded, and the drain region is connected to a device to be protected for electrostatic discharge (ESD);
• a gate layer and a field plate layer on the top surface of the well region between the first end and the second end of the well region, wherein the gate layer and the field plate layer are spaced apart with a gap in between, the gate layer is adjacent to and electrically connected to the source region, and the field plate layer is adjacent to the drain region;
• a first N+ doped region and a first P+ doped region, located in the well region below the gap, and adjacent to each other;
• a conductive layer covering the source region, the drain region, the gate layer, a portion of the field plate layer, and a portion of the first N+ doped region;
• and
• one or more N+ doped regions and one or more P+ doped regions alternately arranged in the field plate layer, wherein the one or more N+ doped regions and the one or more P+ doped regions comprise:
• a second N+ doped region disposed at a first end of the field plate layer, the first end of the field plate layer adjacent to and electrically connected to the drain region;
• a third N+ doped region disposed at a second end of the field plate layer opposite to the first end of the field plate layer, the second end of the field plate layer electrically connected to the first N+ doped region;
• and
• at least one second P+ doped region disposed between the second N+ doped region and the third second N+ doped region;
• wherein at least one PN junction is formed by the one or more N+ doped regions and the one or more P+ doped regions in the field plate layer, the at least one PN junction including a forward PN junction or a reverse PN junction.