Method of manufacturing semiconductor devices having concave lower sidewall portions on gate structures

A method of manufacturing a semiconductor device, the method comprising:

• forming a gate structure on a substrate, the gate structure including a first dielectric pattern containing silicon oxide;
• forming a first gate spacer on an upper portion of a sidewall of the gate structure, the first gate spacer including silicon nitride;
• and
• forming a second gate spacer on an outer sidewall of the first gate spacer and a lower portion of the sidewall of the gate structure, the second gate spacer including silicon nitride,
• wherein a lower surface of the first gate spacer is lower than an upper surface of the first dielectric pattern, and the second gate spacer does not contact an upper portion of a sidewall of the first dielectric pattern but contacts a lower portion of the sidewall of the first dielectric pattern.

A method of manufacturing a semiconductor device, the method comprising:

• forming a first active pattern and a second active pattern on a cell region and a periphery circuit region, respectively, of a substrate;
• forming a first gate structure in an upper portion of the first active pattern, the first gate structure extending in a first direction parallel to an upper surface of the substrate;
• forming a second gate structure on the second active pattern, a sidewall of the second gate structure including:
• a concave lower portion, and
• an upper portion that is vertical with respect to the upper surface of the substrate, forming a spacer structure including:
• a first gate spacer on the upper portion of the sidewall of the second gate structure;
• and
• a second gate spacer on the concave lower portion of the sidewall of the second gate structure and an outer sidewall of the first gate spacer, the second gate spacer contacting a lower surface of the first gate spacer and including silicon nitride, and
• a third gate spacer on an outer sidewall of the second gate spacer;
• forming a bit line structure on a central upper surface of the first active pattern, the bit line structure extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction;
• forming a contact plug structure on each of opposite edge upper surfaces of the first active pattern;
• and
• forming a capacitor on the contact plug structure.