Single-Thread Detection of Valid Synchronization Headers
AssigneeAyDeeKay LLC dba Indie Semiconductor
InventorRakhel Parida
Life of this patent
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AssigneeAyDeeKay LLC dba Indie Semiconductor
InventorRakhel Parida
Estimating the term…
An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.
An integrated circuit, comprising:
A non-transitory computer-readable storage medium for use in conjunction with an electronic device, the computer-readable storage medium storing program instructions, wherein, when executed by the electronic device, the program instructions cause the electronic device to perform one or more operations, comprising:
A method for selectively calculating a baud rate of received signals, comprising:
Dependencies are inferred from the claim text.