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US 2026/0155816 A1Published application
Dual gate cascode drive
AssigneeUnited Silicon Carbide, Inc.
InventorsAnup Bhalla, Xueqing Li
Life of this patent
Estimating the term…
Abstract
A cascode circuit is formed using a high voltage transistor in series with a low voltage transistor. A clamp switch device is used to discharge the gate of the high voltage transistor when the cascode is off. Rate limiting devices may be used control turn on and turn off characteristics of the cascode. Rate limiting devices may be include resistors and/or transistors. The high voltage transistor may be a normally on silicon carbide JFET, for example, and the low voltage transistor may be a silicon MOSFET.
Claims20
A cascode circuit, comprising:
- a junction field-effect transistor, JFET, comprising a JFET drain, a JFET source, and a JFET gate, the JFET drain being connected to a drain of the cascode circuit, wherein the JFET is a normally-on n-type silicon carbide JFET;
- a metal-oxide-semiconductor field-effect transistor, MOSFET, comprising a MOSFET drain, a MOSFET source, and a MOSFET gate, the MOSFET drain being connected to the JFET source and the MOSFET source being connected to a source of the cascode circuit, wherein the MOSFET is a normally-off n-type silicon MOSFET;
- a driver circuit providing outputs comprising a first cascode gate signal and a clamp signal, the first cascode gate signal and the clamp signal being complementary waveforms, wherein the first cascode gate signal is connected to the MOSFET gate;
- and
- a clamp switch controlled by the clamp signal, wherein the clamp switch, when activated, connects the JFET gate to the source of the cascode circuit;
- whereby in a first mode the first cascode gate signal causes the MOSFET to conduct and current flows from the drain of the cascode circuit to the source of the cascode circuit via the JFET and the MOSFET while the clamp switch is off, and
- in a second mode, the clamp signal causes the clamp switch to connect the JFET gate to the MOSFET source when the first cascode gate signal is on.
4 more elements
A cascode circuit, comprising:
- a junction field-effect transistor, JFET, comprising a JFET drain, a JFET source, and a JFET gate, the JFET drain being connected to a drain of the cascode circuit, wherein the JFET is a normally-on n-type silicon carbide JFET;
- a metal-oxide-semiconductor field-effect transistor, MOSFET, comprising a MOSFET drain, a MOSFET source, and a MOSFET gate, the MOSFET drain being connected to the JFET source and the MOSFET source being connected to a source of the cascode circuit, wherein the MOSFET is a normally-off n-type silicon MOSFET;
- connectors receiving driver circuit outputs comprising a first cascode gate signal and a clamp signal, the first cascode gate signal and the clamp signal being complementary waveforms, wherein the first cascode gate signal is connected to the MOSFET gate;
- and
- a clamp switch controlled by the clamp signal, wherein the clamp switch, when activated, connects the JFET gate to the source of the cascode circuit;
- whereby in a first mode the first cascode gate signal causes the MOSFET to conduct and current flows from the drain of the cascode circuit to the source of the cascode circuit via the JFET and the MOSFET while the clamp switch is off, and
- in a second mode, the clamp signal causes the clamp switch to turn on and short the JFET gate to the MOSFET source.
4 more elements
A cascode circuit, comprising:
- a depletion mode field-effect transistor (FET) having a first drain, a first source, and a first gate;
- an enhancement mode FET having a second drain, a second source, and a second gate, wherein the first source is connected to the second drain;
- and
- a clamping device having a first clamping terminal connected to the first gate and a second clamping terminal connected to the second source.
1 more element
Dependencies are inferred from the claim text.