Memory apparatus and operation method of memory apparatus

A memory apparatus comprising:

• a first transistor connected to a first voltage line;
• a second transistor connected between the first transistor and a bit line;
• a third transistor connected to a second voltage line;
• and
• a fourth transistor connected between the third transistor and a word line,
• wherein:
• when a forward enable signal is enabled, turn-on degrees of the third and fourth transistors are reduced;
• and
• when a reverse enable signal is enabled, turn-on degrees of the first and second transistors are reduced.

An operation method of a memory apparatus, the operation method comprising:

• enabling a forward enable signal for causing a forward current to flow through a memory cell;
• turning on, in response to the forward enable signal, first and second switches to provide a current to the memory cell;
• and
• turning on, in response to the forward enable signal, third and fourth switches, through which the current flows from the memory cell, at different turn-on degrees.